![]() Marvell is claiming that its new solution enables a significant power reduction in energy per bit transferred – up to 25% compared to equivalent TSMC 7nm offerings, along with tight power/thermal constraints and a >40dB insertion loss. ![]() ![]() These sorts of connections have a number of measurements to compare them to other 112G solutions: the goal is to not only meet the standard, but offer a solution that uses less power, but also a lower potential error rate, especially for high-speed high-reliability infrastructure applications. Several companies have 112G IP available, however Marvell is the first to enable it in 5nm, ensure it is hardware validated, and offer it for licensing. Current high-speed connections rely on 56G connections, and so moving up to 112G enables double the speed. Modern chip-to-chip networking infrastructure relies on high speed SerDes connections to enable a variety of different protocols at a range of speeds, typically in Ethernet, fiber optics, storage, and connectivity fabrics. Today Marvell is announcing its DSP-based 112G SerDes solution for licensing. We can now add another to that list, but it’s not a standard SoC: here we have IP for a SerDes connection, now validated and ready for licensing in TSMC N5. So far we have three products in the market built on TSMC’s N5 process: the Huawei Kirin 9000 5G SoC, found in the Mate 40 Pro, the Apple A14 SoC, found in the iPhone 12 family, and the Apple M1 SoC, which is in the new MBA/MBP and Mac Mini.
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